A Great Answer

I posted the following question to an interesting article that I read a couple of days ago on EETimes. I wanted to capture the answer to my question because it was so wonderfully succinct and actually differentiated between two types of IP; something totally new to me.

Q.   A great article – it was so good I read it twice. I have a question though – at what stage of the manufacturing process is this FPGA dropped into an SoC?
You mention wire to wire which leads me to think that the integration step occurs post-SOC fabrication.
However, your use of the term eFPGA IP leads me think that the integration occurs in some step prior to the lithography.
Any clarification you can provide would be greatly appreciated.

A. Speedcore is delivered as hard IP in GDSII or OASIS data format and is integrated into the customer ASIC and timing closed before the ASIC is taped out (before lithography). Just for clarification, hard IP is a fixed form of intellectual property that is formatted in a physical design layout and is the required delivery format when performance and area are critical for the IP. This is different than soft IP that is delivered as RTL and the customer synthesizes the IP into gates or physical constructs before integrating it into the ASIC.

As an embedded IP, Speedcore IP connectivity is the same as other integrated IP functions where there are wire connections on the die from the IP to the other functionality in the ASIC. The comment about wire-to-wire connection is to contrast the difference between the embedded FPGA IP and a standalone FPGA that connects to the ASIC through package-PCB-package connections.


  1. IP – Intellectual Property
  2. FPGA – Field Programmable Gate Array (erasable/re-writable logic blocks consisting of AND, OR, NOR, etc. logic gates)
  3. SoC – System on a Chip (CPU, memory, I/O, etc. all on a single chip)
  4. RTL – Register-Transfer Level (RTL is a high level software abstraction of an electronic circuit)
  5. GDSII – Graphic Database System II (contains the planar geometric shapes, text labels, and other information about the layout)
  6. RTL to GDSII – is the design flow that precedes tapeout (creation of the photomask), to the final lithography step
  7. ASIC – Application Specific Integrated Circuit (much like an FPGA except nonerasable. Also called custom silicon).
  8. Speedcore – is the product name

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